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August 2007
HYB18L512320BF-7.5 HYE18L512320BF-7.5
DRAMs for Mobile Applications 512-Mbit SDR Mobile-RAM
Internet Data Sheet
Rev.1.22
Internet Data Sheet
HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
HY[B/E]18L512320BF-7.5 Internet Data Sheet Revision History: Rev.1.22, 2007-08 all Editorial change. Adopted Internet Edition Previous Revision: Rev1.21, 2006-12 all Qimonda update Previous Revision: Rev.1.2 2005-04
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 03292006-D7GM-ZBSS
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Internet Data Sheet
HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
1
1.1
* * * * * * * * * * * * *
Overview
Features
4 banks x 4 Mbit x 32 organization (dual-die) Fully synchronous to positive clock edge Four internal banks for concurrent operation Programmable CAS latency: 2, 3 Programmable burst length: 1, 2, 4, 8 or full page Programmable wrap sequence: sequential or interleaved Programmable drive strength: full, 1/2, 1/4 and 1/8 Auto refresh and self refresh modes Refresh cycles: - 8192 refresh cycles / 64 ms Auto precharge Commercial (-0C to +70C) and Extended (-25C to +85C) operating temperature range Package: - Dual-Die 90-ball PG-TFBGA package (13.0 x 8.0 x 1.2 mm) RoHS Compliant Products1)
Power Saving Features * * * * * Low supply voltages: VDD = 1.70 V to 1.95 V, VDDQ = 1.70 V to 1.95 V Optimized self refresh (IDD6) and standby currents (IDD2 / IDD3) Programmable Partial Array Self Refresh (PASR) Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor Power-Down and Deep Power Down modes
TABLE 1
Performance
Part Number Speed Code Speed Grade Access Time (tACmax) Clock Cycle Time (tCKmin) CL = 2 or 3 CL = 3 CL = 2 - 7.5 133 6.5 7.5 9.5 Unit MHz ns ns ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
TABLE 2
Memory Addressing Scheme
Item Banks Rows Columns Addresses BA0, BA1 A0 - A12 A0 - A8
TABLE 3
Ordering Information
Type
1)
Package PG-TFBGA-90-3 PG-TFBGA-90-3
Description 133 MHz 4 Banks x 4 Mbit x 32 LP-SDRAM 133 MHz 4 Banks x 4 Mbit x 32 LP-SDRAM
Standard Temperature Range HYB18L512320BF-7.5 HYE18L512320BF-7.5 Extended Temperature Range
1) HY[B/E]: Designator for memory products (HYB: Standard temp range, HYE: extended temp. range) 18L: 1.8 V Mobile-RAM 512: 512 MBit density 32: 32 bit interface width B: die revision F: green product -7.5: speed grade(s): min. clock cycle time
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HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
1.2
Pin Configuration
FIGURE 1
Standard Ballout 256-Mbit Mobile-RAM (Top View x32)
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Internet Data Sheet
HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
1.3
Description
The HY[B/E]18L512320BF is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The HY[B/E]18L512320BF achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. Read and write accesses are burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4, 8 or full page) in a programmed sequence. The device operation is fully synchronous: all inputs are registered at the positive edge of CLK. The HY[B/E]18L512320BF is especially designed for mobile applications. It operates from a 1.8 V power supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR). A conventional data-retaining Power Down (PD) mode is available as well as a non-data-retaining Deep Power Down (DPD) mode. The HY[B/E]18L512320BF is housed in a 90-ball PG-VFBGA (x32) package. It is available in Standard (-0 C to +70 C) and Extended (-25 C to +85 C) temperature ranges.
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HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
1.4
Pin Definition and Description
TABLE 4
Pin Description
Ball CLK CKE
Type Input Input
Detailed Function Clock: all inputs are sampled on the positive edge of CLK. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or SUSPEND (access in progress). CKE is synchronous for POWER-DOWN entry and exit and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers, excluding CLK and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during SELF REFRESH. Chip Select: All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple memory banks. CS is considered part of the command code. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Data Inputs/Output: Bi-directional data bus (32 bit) Input/Output Mask: input mask signal for WRITE cycles and output enable for READ cycles. For WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as an output enable and places the output buffers in High-Z state when HIGH (two clocks latency). DQM0 corresponds to the data on DQ0 - DQ7; DQM1 to the data on DQ8 - DQ15; DQM2 to the data on DQ16 - DQ23; DQM3 to the data on DQ24 - DQ31. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: defines the row address during an ACTIVE command cycle. A0 - A8 define the column address during a READ or WRITE command cycle. In addition, A10 (= AP) controls Auto Precharge operation at the end of the burst read or write cycle. During a PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls which bank(s) are to be precharged: if A10 is HIGH, all four banks will be precharged regardless of the state of BA0 and BA1; if A10 is LOW, BA0, BA1 define the bank to be precharged. During MODE REGISTER SET commands, the address inputs hold the op-code to be loaded. I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity: VDDQ = 1.70 V to 1.95 V I/O Ground Power Supply: Power for the core logic and input buffers, VDD = 1.70 V to 1.95 V Ground No Connect
CS RAS, CAS, WE DQ0 - DQ31 DQM0 DQM3
Input Input I/O Input
BA0, BA1
Input
A0 - A12
Input
VDDQ VSSQ VDD VSS
N.C.
Supply Supply Supply Supply -
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HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
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Functional Description
The 512-Mbit Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation.
2.1
Register Definition
2.1.1
Mode Register
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes the selection of a burst length (bits A0-A2), a burst type (bit A3), a CAS latency (bits A4-A6), and a write burst mode (bit A9). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. MRMode Register Definition(BA[1:0] = 00B)
TABLE 5
Mode Register Definition (BA[1:0] = 00B)
Field WB Bits 9 Type w Description Write Burst Mode 0 Burst Write 1 Single Write CAS Latency 010 2 011 3 Note: All other bit combinations are RESERVED.
CL
[6:4]
w
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HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
Field BT
Bits 3
Type w
Description Burst Type 0 Sequential 1 Interleaved Burst Length 000 1 001 2 010 4 011 8 111 full page (Sequential burst type only) Note: All other bit combinations are RESERVED.
BL
[2:0]
w
2.2
Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. EMR Extended Mode Register(BA[1:0] = 10B)
TABLE 6
Extended Mode Register Definition (BA[1:0] = 10B)
Field DS Bits [6:5] Type w Description Selectable Drive Strength 00B DS Full Drive Strength 01B DS Half Drive Strength Note: All other bit combinations are RESERVED. Temperature Compensated Self Refresh XX Superseded by on-chip temperature sensor (see text) Partial Array Self Refresh 000B PASR all banks (default) 001B PASR 1/2 array (BA1 = 0) 010B PASR 1/4 array (BA1 = BA0 = 0) 101B PASR 1/8 array (BA1 = BA0 = RA12 = 0) 110B PASR 1/16 array (BA1 = BA0 = RA12 = RA11 = 0) Note: All other bit combinations are RESERVED.
TCSR PASR
[4:3] [2:0]
w w
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HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
2.3
Function Truth Tables
TABLE 7
Current State Bank n - Command to Bank n
Current State Any Idle
CS H L L L L L
RAS X H L L L L H H L H H L H H H L H
CAS X H H L L H L L H L L H H L L H H
WE X H H H L L H L L H L L L H L L L
Command / Action DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) ACTIVE (select and activate row) AUTO REFRESH MODE REGISTER SET PRECHARGE READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (truncate READ burst, start precharge) BURST TERMINATE READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (truncate WRITE burst, start precharge)
Notes
1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7) 1)2)3)4)5)6)8) 1)2)3)4)5)6)9) 1)2)3)4)5)6)9) 1)2)3)4)5)6)10) 1)2)3)4)5)6)9) 1)2)3)4)5)6)9) 1)2)3)4)5)6)10) 1)2)3)4)5)6)11) 1)2)3)4)5)6)9) 1)2)3)4)5)6)9) 1)2)3)4)5)6)10)
Row Active
L L L
Read (AutoPrecharge Disabled)
L L L L L L L L
Write (AutoPrecharge Disabled)
1)2)3)4)5)6)11) BURST TERMINATE 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3) Current state definitions:Idle:The bank has been precharged, and tRP has been met.Row Active:A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress.Read:A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.Write:A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Table 8.Precharging:Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank is in the "idle" state.Row Activating:Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state.Read with AP Enabled:Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state.Write with AP Enabled:Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. 5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing:Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC ismet, the SDRAM is in the "all banks idle" state.Accessing MR:Starts with registration of a MODE REGISTER SET command and ends when tMRD has beenmet. Once tMRD is met, the SDRAM is in the "all banks idle" state.Precharging All:Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks are in the idle state. 6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle and no bursts are in progress. 8) Same as NOP command in that state. 9) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and READs or WRITEs with Auto Precharge disabled.
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10) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 11) Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
TABLE 8
Current State Bank n - Command to Bank m (different bank)
Current State Any Idle Row Activating, Active, or Precharging CS H L X L L L L Read (AutoPrecharge Disabled) L L L L Write (AutoPrecharge Disabled) L L L L Read(with Auto- L Precharge) L L L Write(with Auto- L Precharge) L L L RAS X H X L H H L L H H L L H H L L H H L L H H L CAS X H X H L L H H L L H H L L H H L L H H L L H WE X H X H H L L H H L L H H L L H H L L H H L L Command / Action DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) Any command otherwise allowed to bank n ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) Notes
1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7)8) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7) 1)2)3)4)5)6)7) 1)2)3)4)5)6) 1)2)3)4)5)6)
1)2)3)4)5)6)7)9) 1)2)3)4)5)6)7)8)9) 1)2)3)4)5)6) 1)2)3)4)5)6) 1)2)3)4)5)6)7)9) 1)2)3)4)5)6)7)9)
1)2)3)4)5)6) PRECHARGE (deactivate row in bank or banks) 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tRC has been met (if the previous state was Self Refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3) Current state definitions:Idle:The bank has been precharged, and tRP has been met.Row Active:A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress.Read:A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated orbeen terminated.Write:A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.Read with AP Enabled:Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state.Write with AP Enabled:Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. 4) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. 5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) All states and sequences not shown are illegal or reserved. 7) READs or WRITEs listed in the Command/Action column include READs or WRITEs with Auto Precharge enabled and READs or WRITEs with Auto Precharge disabled. 8) Requires appropriate DQM masking.
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9) Concurrent Auto Precharge: bank n will start precharging when its burst has been interrupted by a READ or WRITE command to bank m.
TABLE 9
Truth Table - CKE
CKEn-1 L CKEn L Current State Power Down Self Refresh Clock Suspend Deep Power Down L H Power Down Self Refresh Clock Suspend Deep Power Down H L All Banks Idle Bank(s) Active All Banks Idle Read / Write burst H
1) 2) 3) 4) 5) 6)
Command X X X X DESELECT or NOP DESELECT or NOP X X DESELECT or NOP DESELECT or NOP AUTO REFRESH (valid)
Action Maintain Power Down Maintain Self Refresh Maintain Clock Suspend Maintain Deep Power Down Exit Power Down Exit Self Refresh Exit Clock Suspend Exit Deep Power Down Enter Precharge Power Down Enter Active Power Down Enter Self Refresh Enter Clock Suspend
Notes
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4)6) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)
H
See Table 7 and Table 8
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state immediately prior to clock edge n. COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved. DESELECT or NOP commands should be issued on any clock edges occurring during tRC period. Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.
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3
3.1
Electrical Characteristics
Operating Conditions
TABLE 10
Absolute Maximum Ratings
Parameter
Symbol Min.
Values Max. 2.7 2.7 V V V V C C C W mA
Unit
Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Commercial Extended
VDD VDDQ VIN VOUT TC TSTG PD IOUT
-0.3 -0.3 -0.3 -0.3 0 -25 -55 - -
VDDQ + 0.3 VDDQ + 0.3
+70 +85 +150 1.0 50
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
TABLE 11
Pin Capacitances
Parameter Symbol Min. Input capacitance: CLK Input capacitance: all other input Input/Output capacitance: DQ Values Max. 6.0 6.0 5.0 pF pF pF Unit Notes1)2)
CI1 CI2 CIO
3.0 3.0 3.0
1) These values are not subject to production test but verified by device characterization. 2) Input capacitance is measured according to JEP147 with VDD, VDDQ applied and all other pins (except the pin under test) floating. DQ's should be in high impedance state.
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TABLE 12
Electrical Characteristics
Parameter Symbol Min. Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Output leakage current Values Max. 1.95 1.95 V V V V V V A - -
2) 2)
Unit
Notes1)
VDD VDDQ VIH VIL VOH VOL IIL IOL
1.70 1.70 0.8 x VDDQ -0.3
VDDQ + 0.3
0.3 - 0.2 1.0 1.5
VDDQ - 0.2
- -1.0 -1.5
- - - -
1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); All voltages referenced to VSS. VSS and VSSQ must be at same potential. 2) VIH may overshoot to VDD + 0.8 V for pulse width < 4 ns; VIL may undershoot to -0.8 V for pulse width < 4 ns.Pulse width measured at 50% with amplitude measured between peak voltage and DC reference level.
3.2
AC Characteristics
TABLE 13
AC Characteristics
Parameter
Symbol Min.
- 7.5 Max. -- -- 105 133 6.5 -- -- -- -- -- -- 7.0 -- 2 -- -- --
Unit
Notes1)2)3)4)
Clock cycle time Clock frequency Access time from CLK Clock high-level width Clock low-level width Address, data and command input setup time Address, data and command input hold time MODE REGISTER SET command period DQ low-impedance time from CLK DQ high-impedance time from CLK Data out hold time DQM to DQ High-Z delay (READ Commands) DQM write mask latency ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay
CL = 2 CL = 3 CL = 2 CL = 3
tCK fCK tAC tCH tCL tIS tIH tMRD tLZ tHZ tOH tDQZ tDQW tRC tRCD
9.5 7.5 -- -- -- 2.5 2.5 1.5 0.8 2 1.0 3.0 2.5 -- 0 67 19
ns ns MHz MHz ns ns ns ns ns
-- --
5)6)
-- --
7) 7)
tCK
ns ns ns
-- -- --
5)6)
tCK tCK
ns ns
-- --
8) 8)
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HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
Parameter
Symbol Min.
- 7.5 Max. -- 100k -- -- 64 --
Unit
Notes1)2)3)4)
ACTIVE bank A to ACTIVE bank B delay ACTIVE to PRECHARGE command period WRITE recovery time PRECHARGE command period Refresh period (8192 rows)
Self refresh exit time 1 1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); VDD = VDDQ = 1.70 V to 1.95 V;
2) 3) 4) 5) 6) 7) 8)
tRRD tRAS tWR tRP tREF tSREX
15 45 14 19 --
ns ns ns ns ms
8) 8) 9) 8)
-- --
tCK
All parameters assumes proper device initialization. AC timing tests measured at 0.9 V. The transition time tT is measured between VIH and VIL; all AC characteristics assume tT = 1 ns. Specified tAC and tOH parameters are measured with a 30 pF capacity load only as shown in Figure 2. If tT(CLK) > 1 ns, a value of (tT/2 - 0.5) ns has to be added to this parameter. If tT > 1 ns, a value of (tT - 1) ns has to be added to this parameter. These parameter account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round up to next integer. 9) The write recovery time of tWR = 14 ns allows the use of one clock cycle for the write recovery time when fCK 72 MHz. With fCK > 72 MHz two clock cycles for tWR are mandatory. Infineon Technologies recommends to use two clock cycles for the write recovery time in all applications.
FIGURE 2
Measurement with Reference Load
I/O 30 pF
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3.3
Operating Currents
TABLE 14
Maximum Operating Currents
Parameter & Test Conditions
Symbol - 7.5
Unit
Notes1)
Operating current: one bank: active / read / precharge, BL = 1, tRC = tRCmin Precharge power-down standby current: all banks idle, CS VIHmin, CKE VILmax, inputs changing once every two clock cycles Precharge power-down standby current with clock stop: all banks idle, CS VIHmin, CKE VILmax, all inputs stable Precharge non power-down standby current: all banks idle, CS VIHmin, CKE VIHmin, inputs changing once every two clock cycles
IDD1 IDD2P
120 1.2
mA mA
2)3)
2)
IDD2PS IDD2N
1.0 26
mA mA
-
2)
Precharge non power-down standby current with clock stop: IDD2NS all banks idle, CS VIHmin, CKE VIHmin, all inputs stable Active power-down standby current: one bank active, CS VIHmin, CKE VILmax, inputs changing once every two clock cycles
2.0 2.0
mA mA
-
2)
IDD3P
Active power-down standby current with clock stop: IDD3PS one bank active, CS VIHmin, CKE VILmax, all inputs stable Active non power-down standby current: one bank active, CS VIHmin, CKE VIHmin, inputs changing once every two clock cycles
1.5 30
mA mA
-
2)
IDD3N
Active non power-down standby current with clock stop: IDD3NS one bank active, CS VIHmin, CKE VIHmin, all inputs stable Operating burst read current: all banks active; continuous burst read, inputs changing once every two clock cycles
3.0 90
mA mA
-
2)3)
IDD4
Auto-Refresh current: IDD5 tRC = tRCmin, "burst refresh", inputs changing once every two clock cycles Self Refresh current:self refresh mode, CS VIHmin, CKE VILmax, all inputs stable
180
mA
2)
IDD6
See Table 15
-
noted 2) These values are measured with tCK = 7.5 ns 3) All parameters are measured with no output loads.
Deep Power Down current IDD7 50 A - 1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); VDD = VDDQ = 1.70 V to 1.95 V;Recommended Operating Conditions unless otherwise
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Internet Data Sheet
HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
TABLE 15
Self Refresh Currents
Parameter & Test Conditions Max. Temperature 85 C 70 C 45 C 25 C Self Refresh Current: Self refresh mode, half array activation(PASR = 001) 85 C 70 C 45 C 25 C Self Refresh Current: Self refresh mode, quarter array activation(PASR = 010) 85 C 70 C 45 C 25 C Symbol Typ. Values Max. 1200 - - - 940 - - - 800 - - - A - Units Notes1)2)
Self Refresh Current: Self refresh mode, full array activation(PASR = 000)
IDD6
1020 680 450 410 800 570 400 360 680 500 370 340
1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); VDD = VDDQ = 1.70 V to 1.95 V 2) The On-Chip Temperature Sensor (OCTS) adjusts the refresh rate in self refresh mode to the component's actual temperature with a much finer resolution than supported by the 4 distinct temperature levels as defined by JEDEC for TCSR. At production test the sensor is calibrated, and IDD6 max. current is measured at 85C. Typ. values are obtained from device characterization.
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Internet Data Sheet
HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
3.4
Pullup and Pulldown Characteristics
TABLE 16
Half Drive Strength and Full Drive Strength
Voltag e (V)
Half Drive Strength Pull-Down Current (mA) Nominal Low Nominal High 0.0 20.5 28.5 32.0 33.5 35.0 35.3 35.5 35.7 35.9 Pull-Up Current (mA) Nominal Low -19.7 -18.8 -18.2 -17.6 -16.7 -9.4 -6.6 -1.8 3.8 9.8 Nominal High -33.4 -32.0 -31.0 -29.9 -28.7 -20.4 -17.1 -11.4 -4.8 2.5
Full Drive Strength Pull-Down Current (mA) Nominal Low 0.0 30.2 40.5 43.9 45.2 46.9 47.2 47.5 47.7 48.0 Nominal High 0.0 41.0 57.0 64.0 67.0 70.0 70.5 71.0 71.4 71.8 Pull-Up Current (mA) Nominal Low -39.3 -37.6 -36.4 -35.1 -33.3 -18.8 -13.2 -3.5 7.5 19.6 Nominal High -66.7 -63.9 -61.9 -59.8 -57.3 -40.7 -34.1 -22.7 -9.6 5.0
0.00 0.40 0.65 0.85 1.00 1.40 1.50 1.65 1.80 1.95
0.0 15.1 20.3 22.0 22.6 23.5 23.6 23.8 23.9 24.0
The above characteristics are specified under nominal process variation / conditionTemperature (Tj): Nominal = 50 C, VDDQ: Nominal = 1.80 V
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Internet Data Sheet
HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
4
Package Outlines
FIGURE 3
PG-TFBGA-90-3 (Plastic Thin Fine Ball Grid Array Package)
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Internet Data Sheet
HY[B/E]18M256[16/32]0DF-5/6 512-Mbit Mobile-RAM
List of Figures
Figure 1 Figure 2 Figure 3 Standard Ballout 256-Mbit Mobile-RAM (Top View x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Measurement with Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PG-TFBGA-90-3 (Plastic Thin Fine Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Internet Data Sheet
HY[B/E]18M256[16/32]0DF-5/6 512-Mbit Mobile-RAM
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Extended Mode Register Definition (BA[1:0] = 10B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current State Bank n - Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current State Bank n - Command to Bank m (different bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth Table - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Self Refresh Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Half Drive Strength and Full Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Internet Data Sheet
HY[B/E]18L512320BF-7.5 512-Mbit Mobile-RAM
Table of Contents
1 1.1 1.2 1.3 1.4 2 2.1 2.1.1 2.2 2.3 3 3.1 3.2 3.3 3.4 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 5 6 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pullup and Pulldown Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 16 18
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Internet Data Sheet
Edition 2007-08 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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